Organizers
The workshop “Verilog® HDL and FPGA  Prototyping”  is organized by Mr. Cejo K. L., Chairperson, IEEE Kerala Section GOLD Affinity Group with the IEEE Student Branch of Model Engineering College, Thrikkakara, Kochi.  Model Engineering College, Thrikkakara is a premier institute of engineering that has carved a niche for itself in the field of technical education in a very short span of time. Since its inception in 1989, under the aegis of the Institute of Human Resource Development, IHRD (Government of Kerala undertaking), the college has made its presence felt in the technical horizon of the state. The college offers engineering courses in Computer Science & Engineering, Electronics & Communication Engineering and Electronics & Biomedical Engineering. All eligible programs offered by the college are accredited by National Board of Accreditation (NBA). The college is also funded by Technical Education Quality Improvement Programme (TEQIP) of Government of India.

Objectives
IEEE, the world's leading professional association for the advancement of technology, is celebrating 125 years of "Engineering the Future". The workshop is organized as part of the 125^th anniversary celebrations of IEEE. Hardware description languages (HDLs) have deeply influenced the VLSI design flow of integrated circuits. Verilog® HDL is a widely used HDL for FPGA and ASIC designs. Field Programmable Gate Arrays (FPGAs) enable rapid prototyping and implementation of reconfigurable digital hardware. Advanced FPGA devices can accommodate million gate logic designs for signal processing, high speed communication systems and embedded systems applications. The course aims to impart Verilog coding skills for FPGA based system design. 

• Verilog® HDL simulation and synthesis
• Free and open source EDA tools – GPLCver, Icarus Verilog and GTKWave
• Verilog RTL Coding Guidelines
• Hands-on sessions on rapid prototyping using Xilinx FPGA devices